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low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer ics8534-01 idt? / ics? 3.3v lvpecl fanout buffer 1 ICS8534AY-01 rev. a december 6, 2007 general description the ics8534-01 is a low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the ics8534-01 has two selectable clock inputs. the clk, nclk pair can accept most standard differential input levels. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels. the device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the oe pin. the ics8534-01?s low output and part-to-part skew characteristics make it ideal for wo rkstation, server, and other high performance clock distribution applications. features ? twenty-two differential lvpecl outputs ? selectable different ial clk/nclk or lvpecl clock inputs can accept the following differential input levels: lvds, lvpecl, lv h s t l ? clk/nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? pclk/npclk supports the follo wing input levels: lvpecl, cml, sstl ? maximum output frequency: 500mhz ? output skew: 100ps (maximum) ? translates any single-ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? additive phase jitter, rms): 0.04ps (typical) ? full 3.3v supply mode ? 0c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages. hiperclocks? ic s block diagram pin assignment q0:q21 nq0:nq21 clk_sel oe clk nclk pclk npclk d le q 0 1 22 22 pullup pullup pulldown pulldown pullup/pulldown pullup/pulldown 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cco nq6 q6 q5 nq4 q4 nq3 nq5 v cco nq2 q3 q2 nq1 q1 nq0 q0 nq14 q15 nq15 q14 q16 v cco nq16 q17 v cco nq17 q18 nq18 q19 nq19 q20 nq20 v cco q21 nc nc nc v cc clk nclk clk_sel pclk npclk v cco v ee oe nc nq21 q7 nq7 q8 nq8 q9 nq9 q10 nq10 v cco qc11 nq11 q12 nq12 nq13 q13 v cco ics8534-01 64-lead tqfp e-pad 10mm x 10mm x 1.0mm package body y package top view
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 2 ICS8534AY-01 rev. a december 6, 2007 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 16, 17, 32, 33, 48, 49, 64 v cco power output supply pins for lvpecl outputs. 2, 3, 12, 13 nc unused no connect. 4v cc power core supply pin for lvpecl outputs. 5 clk input pulldown non-inverting differential clock input. 6 nclk input pullup/ pulldown inverting differential clock input. pulled to 2 / 3 v cc . 7 clk_sel input pullup clock select input. when high, selects pclk, npclk inputs. when low, selects clk, nclk inputs. lvcmos / lvttl interface levels. 8 pclk input pulldown non-inverting di fferential lvpecl clock input. 9 npclk input pullup/ pulldown inverting differential lvpec l clock input. pulled to 2 / 3 v cc . 10 v ee power negative supply pin. 11 oe input pullup output enable. when logic high, th e outputs are enabled (default). when logic low, the outputs are disa bled and drive differential low: qx = low, nqx = high. lvcmos / lvttl interface levels. 14, 15 nq21, q21 output diffe rential clock outputs. lvpecl interface levels. 18, 19 nq20, q20 output diffe rential clock outputs. lvpecl interface levels. 20, 21 nq19, q19 output diffe rential clock outputs. lvpecl interface levels. 22, 23 nq18, q18 output diffe rential clock outputs. lvpecl interface levels. 24, 25 nq17, q17 output diffe rential clock outputs. lvpecl interface levels. 26, 27 nq16, q16 output diffe rential clock outputs. lvpecl interface levels. 28, 29 nq15, q15 output diffe rential clock outputs. lvpecl interface levels. 30, 31 nq14, q14 output diffe rential clock outputs. lvpecl interface levels. 34, 35 nq13, q13 output diffe rential clock outputs. lvpecl interface levels. 36, 37 nq12, q12 output diffe rential clock outputs. lvpecl interface levels. 38, 39 nq11, q11 output diffe rential clock outputs. lvpecl interface levels. 40, 41 nq10, q10 output diffe rential clock outputs. lvpecl interface levels. 42, 43 nq9, q9 output diffe rential clock outputs. lvpecl interface levels. 44, 45 nq8, q8 output diffe rential clock outputs. lvpecl interface levels. 46, 47 nq7, q7 output diffe rential clock outputs. lvpecl interface levels. 50, 51 nq6, q6 output diffe rential clock outputs. lvpecl interface levels. 52, 53 nq5, q5 output diffe rential clock outputs. lvpecl interface levels. 54, 55 nq4, q4 output diffe rential clock outputs. lvpecl interface levels. 56, 57 nq3, q3 output diffe rential clock outputs. lvpecl interface levels. 58, 59 nq2, q2 output diffe rential clock outputs. lvpecl interface levels. 60, 61 nq1, q1 output diffe rential clock outputs. lvpecl interface levels. 59 nq0, q0 output different ial clock outputs. l vpecl interface levels.
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 3 ICS8534AY-01 rev. a december 6, 2007 table 2. pin characteristics function table table 3. control input function table. figure 1. oe timing diagram symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 37 k ? r pulldown input pulldown resistor 75 k ? inputs outputs oe clk_sel q0:q21 nq0:nq21 00lowhigh 01lowhigh 1 0 clk nclk 1 1 pclk npclk enabled disabled nclk, npclk clk, pclk oe nq0:nq21 q0:q21
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 4 ICS8534AY-01 rev. a december 6, 2007 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma package thermal impedance, ja 22.3 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current 230 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current oe, clk_sel v cc = v in = 3.465v 5 a i il input low current oe, clk_sel v cc = 3.465v, v in = 0v -150 a
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 5 ICS8534AY-01 rev. a december 6, 2007 table 4c. differential dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 85 c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4c. lvpecl dc characteristics, v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 85 c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . note 3: outputs terminated with 50 ? to v cco ? 2v. symbol parameter test conditio ns minimum typical maximum units i ih input high current clk v cc = v in = 3.465v 150 a nclk v cc = v in = 3.465v 5 a i il input low current clk v cc = 3.465v, v in = 0v -5 a nclk v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input vo ltage; note 1, 2 v ee + 0.5 v cc ? 0.85 v symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk v cc = v in = 3.465v 150 a npclk v cc = v in = 3.465v 5 a i il input low current pclk v cc = 3.465v, v in = 0v -5 a npclk v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.3 1.0 v v cmr common mode input vo ltage; note 1, 2 v ee + 1.5 v cc v v oh output high voltage; note 3 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 3 v cco ? 2.0 v cco ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 6 ICS8534AY-01 rev. a december 6, 2007 ac electrical characteristics table 5. v cc = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 85c all parameters measured at f max unless noted otherwise. special thermal considerations may be required. see applications section. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the sa me supply voltage and with equal load conditions. note 3: this parameter is defined in accordance with jede c standard 65. measured at the out put differential cross points. note 4: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns at the same temperature. using the same type of inputs on each devi ce, the outputs are measured at the differential cross points. note 5: driving only one input clock. symbol parameter test conditions minimum typical maximum units f max output frequency 500 mhz t pd propagation delay; note 1 ? 500mhz 2.0 3.0 ns t sk(o) output skew; note 2, 3 100 ps t sk(pp) part-to-part skew; note 3, 4 700 ps tjit buffer additive phase jitter, rms, refer to additive phase jitter section; note 5 integration range: 12khz - 20mhz 0.4 ps t r / t f output rise/ fall time 20% to 80% 200 700 ps t s setup time 1 ns t h hold time 0.5 ns odc output duty cycle ? 266mhz 48 52 % 266 < ? 500mhz 46 54 %
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 7 ICS8534AY-01 rev. a december 6, 2007 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m additive phase jitter, rms @ 156.25mhz 12khz to 20mhz = 0.04ps (typical) offset frequency (hz) ssb phase noise dbc/hz
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 8 ICS8534AY-01 rev. a december 6, 2007 parameter measureme nt information 3.3v lvpecl output load ac test circuit part-to-part skew propagation delay differential input level output skew output rise/fall time scope qx nqx lvpecl v ee v cc, 2v - 1.3v 0.165v v cco t sk(pp) part 1 part 2 nqx qx nqy qy t pd nclk, npclk clk, pclk nq0:nq21 q0:q21 v cc v ee v cmr cross points v pp nclk, npclk clk, pclk nqx qx nqy qy t sk(o) clock outputs 20% 80% 80% 20% t r t f v swing
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 9 ICS8534AY-01 rev. a december 6, 2007 parameter measurement in formation, continued output duty cycle/pulse width/period application information wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ended signal driving differential input - t pw t period t pw t period odc = x 100% nq0:nq21 q0:q21 v_ref single ended clock input v cc clk, pclk nclk. npclk r1 1k c1 0.1u r2 1k
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 10 ICS8534AY-01 rev. a december 6, 2007 differential clock input interface the clk /nclk accepts lvpecl, lvds, lvhstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. hiperclocks clk/nclk input driven by an idt open collector cml driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3e. hiperclocks clk/nclk input driven by an sstl driver figure 3b. hiperclocks clk/nclk input driven by a built-in pullup cml driver figure 3d. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver with ac couple figure 3f. hiperclocks clk/nclk input driven by a 3.3v lvds driver clk nclk hiperclocks cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120 3.3v r1 100 cml built-in pullup clk nclk 3.3v hiperclocks zo = 50 ? zo = 50 ? r1 125 r2 125 r5 100 - 200 r6 100 - 200 clk nclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v hiperclocks c1 c2 3.3v r1 100 lvds clk nclk 3.3v hiperclocks zo = 50 ? zo = 50 ?
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 11 ICS8534AY-01 rev. a december 6, 2007 lvpecl clock input interface the pclk /npclk accepts lvpecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. hiperclocks pclk/npclk input driven by an open collector cml driver figure 4c. hiperclocks pclk/npclk input driven by a 3.3v lvpecl driver figure 4e. hiperclocks pclk/npclk input driven by an sstl driver (delete this figure figure 4b. hiperclocks pclk/npclk input driven by a built-in pullup cml driver figure 4d. hiperclocks pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 4f. hiperclocks pclk/npclk input driven by a 3.3v lvds driver pclk npclk hiperclocks pclk/npcl k cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl hiperclocks input pclk npclk hiperclocks pclk/npclk sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120 3.3v r1 100 cml built-in pullup pclk npclk 3.3v hiperclocks pclk/npclk zo = 50 ? zo = 50 ? r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v hiperclocks pclk/npclk c1 c2 pclk npclk 3.3v hiperclocks pclk/npclk r3 1k r4 1k r1 1k r2 1k 3.3v zo = 50 ? zo = 50 ? 3.3v c1 c2 r5 100 lvds
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 12 ICS8534AY-01 rev. a december 6, 2007 recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. pclk/npclk inputs for applications not requiring the use of the differential input, both pclk and npclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 13 ICS8534AY-01 rev. a december 6, 2007 epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology. figure 6. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 14 ICS8534AY-01 rev. a december 6, 2007 power considerations this section provides information on power dissipa tion and junction temperature for the ics5334-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics534-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 230ma = 796.95mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, t he total power is 22 * 30mw = 660mw total power_ max (3.8v, with all outputs swit ching) = 796.95mw + 660mw = 153.08mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming 0 air flow and a multi-layer board, the appropriate value is 17.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.457w * 17.2c/w = 110.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ja for 64 lead tqfp, forced convection ja by velocity linear feet per minute 0200500 multi-layer pcb, jedec standard test boards 22.3c/w 17.2c/w 15.1c/w
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 15 ICS8534AY-01 rev. a december 6, 2007 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50 ?
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 16 ICS8534AY-01 rev. a december 6, 2007 reliability information table 7. ja vs. air flow table for a 64 lead tqfp, e-pad transistor count the transistor count for ics8534-01 is: 1474 ja vs. air flow linear feet per minute 0200500 multi-layer pcb, jedec standard test boards 22.3c/w 17.2c/w 15.1c/w
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 17 ICS8534AY-01 rev. a december 6, 2007 package outline and package dimension package outline - y suffix for 64 lead tqfp, e-pad table 8. package dimensions for 64 lead tqfp, e-pad reference document: jedec publication 95, ms-026 jedec variation: acd all dimensions in millimeters symbol minimum nominal maximum n 64 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 12.00 basic d1 & e1 10.00 basic d2 & e2 7.50 ref. d3 & e3 4.5 5.0 5.5 e 0.50 basic l 0.45 0.60 0.75 0 7 ccc 0.08 -hd version exposed pad down
ics8534-01 low skew, 1-to-22 differential-to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 18 ICS8534AY-01 rev. a december 6, 2007 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature ICS8534AY-01 ICS8534AY-01 64 lead tqfp tray 0 c to +85 c ICS8534AY-01t ICS8534AY-01 64 lead tqfp 500 tape & reel 0 c to +85 c ICS8534AY-01lf ICS8534AY-01lf ?lead-free? 64 lead tqfp tray 0 c to +85 c ICS8534AY-01lft ICS8534AY-01lf ?lead-free? 64 lead tqfp 500 tape & reel 0 c to +85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserv es the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics8534-01 low skew, 1-to-22 differential -to-3.3v lvpecl fanout buffer idt? / ics? 3.3v lvpecl fanout buffer 19 ICS8534AY-01 rev. a december 6, 2007 revision history sheet rev table page description of change date a 15 updated package outline and package dimensions. 11/19/04 a t9 1 12 13 18 features section - added lead-free bullet. added recommendations for unused input and output pins section. updated epad thermal release path section. ordering information table. added lead-free part number, marking and note. updated format throughout the datasheet. 12/06/07
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